HOME > Article > DetailA thread-level parallelization of pairwise additive potential and force calculations suitable for current many-core architecturesYoshimichi Andoh, Soichiro Suzuki, Satoshi Ohshima, Tatsuya Sakashita, Masao Ogino, Takahiro Katagiri, Noriyuki Yoshii, Susumu Okazaki. The Journal of Supercomputing 74 [6] 2449-2469. 2018.https://doi.org/10.1007/s11227-018-2272-2 NIMS author(s)ANDOH, YoshimichiFulltext and dataset(s) on Materials Data Repository (MDR)Created at: 2020-12-21 12:29:52 +0900Updated at: 2024-04-02 01:16:21 +0900