Low Dark Noise and 8.5k e− Full Well Capacity in a 2-Layer Transistor Stacked 0.8μ m Dual Pixel CIS with Intermediate Poly-Si Wiring
Y. Satake, Y. Tanaka, S. Sato, M. Takase, M. Hoyano, S. Kasukawa, M. Tomita, Y. Kikuchi, J. Yamamoto, K. Tokuhiro, K. Furumoto, H. Sugino, Y. Murakawa, S. Yamazaki, H. Mizuno, H. Tomita, N. Yamada, T. Hirano, Y. Kitano.
