Development of multi-valued logic devices: As shown in Figure 1, a pn heterointerface is formed at the center of this transistor, exhibiting a unique characteristic where the drain current sharply increases and decreases. By utilizing negative differential resistance—where current decreases as voltage increases—we successfully demonstrated a ternary logic device representing three operational values (0, 1, 2). Compared with conventional binary logic (0, 1) elements, ternary logic allows drastic increase in integration density. Furthermore, quaternary logic devices with four operational values (0, 1, 2, 3) have recently been realized.

Development of multi-valued logic-in-memory: As shown in Fig. 2, we demonstrated the operation of a multi-valued logic-in-memory device in which the two functions of computation and memory are operated by a single element, and both functions are multi-valued simultaneously. While the separation of computation and storage in conventional von Neumann architecture devices poses a bottleneck for device functionality, this achievement goes beyond merely solving that issue. By successfully multi-valuing both computation and memory simultaneously, this result leads to a dramatic improvement in integration density and recording density, as well as the suppression of power consumption.